Data transferring device and video game apparatus using the same

ABSTRACT

A data transferring device transfers data via data buses between a plurality of data transmitting and receiving devices, and can continuously transfer data read out from a memory. The data transferring device includes a DMA (Dynamic Memory Access), which writes readable data in the memory per a plurality of bytes from a byte boundary. The data transferring device has the advantageous to be applied to a video game apparatus. The data transferring device has a basic structure having a plurality of data transmitting and receiving devices, a plurality of bus interface circuits connected via buses corresponding to each of the plurality of the data transmitting and receiving devices a direct memory access circuit (DMA), which transfers the data transmitted to one bus interface circuit to another bus interface circuit. Further, the plurality of bus interface circuits divide and unite data in correspondence with size of the connected buses to transfer the data to another bus interface circuit.

FIELD OF THE INVENTION

The present invention relates to a data transferring device. Moreparticularly, it relates to a device, which transmits and receives datathrough data buses between a plurality of data transmitters. A datatransmitting and receiving device is here defined as a circuit device,which can send out to and receive the data from the data buses.Therefore, a memory device may be also considered as a data transmittingand receiving device. Further, the present invention relates to a datatransferring device, which can continuously transfer data read out fromthe memory device. Furthermore, the present invention relates to a datatransferring device to write data from a byte boundary to the memorydevice. Additionally, it relates to a video game apparatus employing theabove-described transferring device.

BACKGROUND OF THE INVENTION

Data processing equipment, such as a video game apparatus, i.e., aninformation processing apparatus, includes a plurality of functionalcircuits, each of which is assigned to perform a specific function andhas a data transmitting and receiving device as defined above.

It is necessary to transmit and receive data with a high speed between aplurality of data transmitting and receiving devices, for example,between a CPU and a memory device.

Therefore, a plurality of CPUS, memory devices, or the like, as datatransmitting and receiving devices are connected to a data bus. Datatransmitting is performed via the data buses between the datatransmitting and receiving devices. In a conventional system fortransmitting addresses via the buses, all of data transmitting andreceiving devices, such as a CPU, a RAM, and a VDP (video displayprocessor), are connected to one data bus.

Therefore, in the conventional system having such a structure as theabove, data existing on the data bus should be only one at a certaintiming to prevent from collision of data.

Accordingly, it becomes a problem not to concurrently transfer variouskinds of data between, for example, a CPU and a RAM, and an externalmemory and a VDP. Further, when there are differences between bus sizes,with which data transmitting and receiving devices can interface, eachdata transmitting and receiving device should have an own interfacecircuit to interface with a common bus, that is, a CPU bus.

On the other hand, in a video game apparatus, i.e., a data processor oran information processing apparatus, an external storage, that is, amemory cartridge is detachably connected to a console unit of the videogame apparatus, and data read out from the memory cartridge istransferred to the console unit via a bus.

In recent years, a processing speed of CPUs has been increased, andconsequently, the speed of transferring data in a system has also becomefast.

In such a case, however, it should be considered that the high speed oftransferring data causes leakage of impediment radio waves to theoutside. FCC (Federal Communication Commission), or the like, haspredetermined a standard to regulate the leakage of the impediment radiowaves.

Therefore, it becomes a problem not to make a high speed in transferringdata on the bus to the console unit from an external storage device,which is detachably connected to the console unit, due to such the FCCstandard.

Meanwhile, as described above, in a data processor, such as a video gameapparatus, it is required that data can be transferred with a high speedbetween a CPU and a memory, which are considered as a functionalcircuit.

In this respect, to reduce a functional load on a CPU, it has beenintroduced to employ a direct memory access device (DMA) fortransmitting or transferring data.

FIG. 1 is to explain an operation of a conventional system employing thedirect memory access device. FIG. 2 illustrates an operational timingchart for the system of FIG. 1.

FIG. 1 shows a structural example of a video game apparatus, whichincludes a direct memory access circuit (DMA) 60, a CPU 61 for executingand controlling a game program, a work RAM 62 for storing data duringgame execution, and a video processor (VDP) 63 for controlling scrollpictures and displayed sprites or models. A data bus 64 is connectedwith each of the above-described circuits.

With this structure, the operation of transferring data sent from theRAM 62 to the VDP 63 will be described, as referring to the timing chartshown in FIG. 2. The DMA 60 sends out an address to read data out fromthe RAM 62, as synchronized with a clock signal CLK, and sends the readout data to an address bus, which is not shown in the diagram, but isprovided independently from the data bus 64 (see a 1 of FIG. 2).

Data are read out from the RAM 62 on the bus 64 according to the readaddress (b 2 of FIG. 2). The data read out from the RAM 62 on the bus 64is temporally stored in a temporal register in the DMA 60, not shown inthe diagram, (c 3 of FIG. 2).

Additionally, a write address is outputted from the DMA 60 to theabove-described address bus 4 of FIG. 2). The content in the temporalresistor in the DMA 60 is outputted to the bus 64 simultaneously withthe write address (b 5 of FIG. 2).

Consequently, the data read out from the RAM 62 on the bus 64 arewritten to the VDP 63 according to the write address outputted to theaddress bus (b 6 of FIG. 2).

In this way, both of the address bus and the data bus should be employedwith time-division according to FIG. 2, for accessing the RAM 62 and theVDP 63. Therefore, it is impossible to continuously read and write datafrom the RAM 62 and to the VDP 63.

On the contrary, in recent years, a synchronous DRAM, of which an inputand an output are synchronized with a clock signal has been employed asa RAM 62 to transfer data with a high speed. However, with theabove-described conventional structure, it is impossible to use afeature of continuously reading data out from the synchronous DRAM.

Concurrently, it is impossible to continuously process data. Therefore,it is also difficult to process the data with a high speed in the VDP63.

In the above-described video game apparatus, the RAM should include aboundary, which is defined by a unit of a plurality of bytes independence on a bit width of the CPU, and it is, therefore, necessary toread out the data by each unit of the plurality of bytes (hereinafter,the unit is referred to as a long-word at need). Therefore, a bit mapmemory, which is used for displaying a video image as a set of pixels,includes a boundary of a unit including a plurality of bytes.

FIG. 3A shows a data structural example 81 in the conventional RAM. Forexample, when a RAM having a width of 32 bits (four bytes) is taken asan example, data are read out from the RAM, as one unit of 4 bytes.

Therefore, a long-word boundary 83 exists per one unit of four bytes,which are the plurality of bytes. In FIG. 3A, data "A", "B", "C", and"D" are respectively stored in the 0th byte, the 1th byte, the 2nd byte,and the 3rd byte. Then, the data "ABCD" can be read as a long word atonce.

Over against this, a data structural example 82 of the bit map memoryshown in FIG. 3B also includes a long-word boundary 83 per a unit of aplurality of bytes, since data are written per a unit of a plurality ofbytes.

If one pixel is expressed with 8 bits (1 byte), 4 pixels arrangedhorizontally in the bit map are expressed with one long-word (4 bytes).Accordingly, a long-word boundary 83 is present per 4 pixels in ahorizontal direction.

With this memory structure, four times of accessing should be required,in order to write data for 16 pixels, when writing data from thelong-word boundary 83. However, in the bit map memory, it is required towrite per a pixel, i.e., a byte, to construct display images freely. Inthis case, as shown in FIG. 3B, it is required for writing data from thebyte boundary 84 to write the data per a byte.

Therefore, it becomes a problem such that 16 times of access processingare required to write data for 16 pixels, because of writing from thebyte boundary 84 and writing per a byte, thus causing delay in atransferring speed of the DMA.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a datatransferring device, which can concurrently transfer data between aplurality of data transmitting and receiving devices.

It is a more specific object of the present invention to provide a datatransferring device, which has no need to provide an interface circuitfor interfacing with a CPU bus per a data transmitting and receivingdevice, even if bus sizes are different for a plurality of datatransmitting and receiving devices.

More particularly, it is an object of the present invention to provide avideo game apparatus employing a data transferring device, which canemploy a high speed CPU, and transmit data read out from an externalstorage device, which is detachably connected to a console unit of thevideo game apparatus, to the high speed CPU via a bus.

It is another object of the present invention to provide a datatransferring device, which can transmit data employing a feature of asynchronous DRAM, which can read out data continuously.

It is still another object of the present invention to provide a datatransferring device employing a DMA, which can reduce the times ofaccessing to a bit map memory, even if data are written to a bit mapmemory from a byte boundary.

It is a further object of the present invention to provide a datatransferring device employing a DMA, which can reduce a transmissiontime when writing data from a byte boundary.

It is a still further object of the present invention to provide a videogame apparatus employing a data transferring device according to thepresent invention, which can make the scrolling and sprite processingwith a high speed in a video display processor.

To realize the above-described objects, a data transferring deviceaccording to the present invention is connected to a plurality of datatransmitting and receiving devices via corresponding external buses, fortransferring data between the plurality of the data transmitting andreceiving devices, and comprises a plurality of bus interface circuits,to which each of the corresponding external buses is connected; and adirect memory access circuit operatively connected to the plurality ofbus interface circuits for transferring the data between said theplurality of bus interface circuits.

Further, in the data transferring device according to the presentinvention, at least two of the plurality of bus interface circuits arerespectively connected to external buses, each having a different bussize from that of the other, and a data processing circuit for dividingor uniting data to accord with the bus size of either one, to which thedata are transferred, of the external buses, when the data aretransferred between the external buses, each having different bus sizes.

Additionally, in the data transferring device according to the presentinvention, the plurality of bus interface circuits and the direct memoryaccess circuit are connected by an internal bus, which has a bus sizecorresponding to the maximum one within the bus sizes, which saidexternal buses have.

In the data transferring device according to the present invention, thedata processing circuit divides data on a first external bus having afirst bus size and sequentially transfers the divided data to a secondexternal bus having a second bus size, which is smaller than the firstbus size according to the plurality of timings.

On the contrary, in the data transferring device according to thepresent invention, the data processing circuit unites data for aplurality of timings on a second external bus having a second bus sizeand sequentially transfers the united data to a first external bushaving a first bus size, which is larger than the second bus size.

Further, an information processing apparatus according to the presentinvention comprises a data transferring device, a plurality of datatransmitting and receiving devices, and a plurality of external busesfor connecting the data transferring device to corresponding one of theplurality of the data transmitting and receiving devices, said datatransferring device having a plurality of bus interface circuits, towhich each of the corresponding external buses is connected, and adirect memory access circuit operatively connected to the plurality ofthe bus interface circuits for transferring the data between said theplurality of the bus interface circuits, and a bus size of one externalbus connected to one of the data transmitting and receiving devicesbeing the minimum size within the external buses connected to the datatransferring device.

In the present invention, as described above, the data transferringdevice includes a system control unit connected to a plurality of datatransmitting and receiving devices via corresponding buses.

The data transferring device is constituted with a plurality of businterface circuits, to which the corresponding buses are connected, anda direct memory access (DMA) circuit, which transfers data sent to theone bus interface circuit to another bus interface circuit, and theplurality of bus interface circuits divide and unite the data incorrespondence with the bus sizes of connected buses.

Accordingly, it becomes easy to transfer data between the datatransmitting and receiving devices, even if the bus sizes of theconnected buses are different. Further, since the plurality of businterface circuits, to which corresponding buses are connected, areprovided, there is no necessary to provide any interface circuit on eachof the data transmitting and receiving devices to respectively interfacewith a CPU.

Further, a data transferring device, which transfers data with the useof a characteristic of a synchronous DRAM, which can continuously readdata, is connected to a first external bus and a second external bushaving 1/n (n means positive integer) of the bus size of the firstexternal bus, and includes first and second bus interface circuits, towhich the first and second external buses are respectively connected, adirect memory access circuit for transferring data on the first externalbus, which are transmitted to the first bus interface circuit, to thesecond bus interface circuit, and an internal bus connected to the firstand second bus interface circuits and the direct memory access circuit,having the same bus size as that of the first external bus, the firstbus interface circuit converting the data, which are continuouslytransmitted with a predetermined period synchronized with a clocksignal, on the first external bus to the data having 1/n of thepredetermined period and outputting the converted data to the internalbus, the direct memory access circuit shifting the data by a 1/n periodand re-translating the shifted data to the internal bus, and the secondbus interface circuit taking the data of 1/n of the predeterminedperiod, which are re-transmitted from the direct memory access circuitto the internal bus, making the taken data to a continuous data sequencewith the 1/n period, and re-translating the continuous data sequencewith the 1/n period to the second external bus.

As described above, in the present invention, the bus interface circuitsynchronizes with a clock to output data on the first bus to an internalbus of the system control unit, and the second bus interface circuittransmits the data having 1/n of the predetermined period from thedirect memory access circuit (DMA) to the second bus within thepredetermined period.

It therefore, becomes possible according to the present invention tocontinuously send data having a predetermined period on the first bus,to the second bus at the predetermined period.

Further, the data transferring device further includes a synchronousDRAM, of which inputs and outputs are synchronized with a clock,connected to the first external bus to read data output from thesynchronous DRAM and send the data to the first bus interface circuit.Therefore, it is possible to employ a feature of continuously readingdata of the synchronous DRAM.

More particularly, by employing the above-described positive integer nas 2, the second interface circuit can send data taken to the directmemory access circuit (DMA) as upper and lower data of 1/2 data sequenceto the second bus.

Even if the data is written from a byte boundary to the bit map memory ,a data transferring device employing a DMA, which can reduce times ofaccess processing, according to the present invention includes a firstlatch circuit for latching n bytes of data, which are read in, a secondlatch circuit operatively connected to the first latch circuit forlatching (n-1) bytes of the data output from the first latch circuit,and a selector supplied with the n bytes of data latched in the firstlatch circuit and combined n bytes, which are formed by combining thelatched n byte data of the first latch circuit with the latched (n-1)byte data of the second latch circuit and shifting sequentially by onebyte, for selecting a desired set of n bytes of data from the supplied nbytes.

Therefore, in the DMA, data read per a plurality of bytes from the firstmemory is shifted to transfer to the second memory per a plurality ofbytes. Accordingly, it is becomes possible to write from the byteboundary on transferring per a plurality of bytes in the second memory.For example, at most, 5 times of access processing are required totransfer data for 16 pixels, thus sharply reducing a transmission time.

Further, it can be realized to constitute the circuit with a simplestructure, such as a pair of latch circuits and a selector.

Furthermore, as the selector selects data, it can be improved to reducedelay time for the shift operation, thus transferring data with a higherspeed.

The objects, features and advantageous of the present invention will beapparent from the following detailed description of the preferredembodiment of the present invention with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an explanatory operational diagram of a conventionalexample corresponding to the second feature of the present invention.

FIG. 2 shows an operational timing chart corresponding to FIG. 1.

FIGS. 3A and 3B are an explanatory diagram of a conventional examplecorresponding to the third feature of the present invention.

FIG. 4 is a block diagram of an embodiment of the present invention.

FIG. 5 shows a structural example of each bus shown in FIG. 4.

FIG. 6 is a structural block diagram of a system control unit shown inFIG. 4.

FIG. 7 illustrates an operational timing chart of the embodiment of thepresent invention.

FIG. 8 illustrates an operational timing chart of the embodiment of thepresent invention.

FIG. 9 illustrates a signal structural example of the embodiment of thepresent invention.

FIG. 10A shows a content of a bus 6 shown in FIG. 9.

FIG. 10B shows a timing chart of the bus 6 shown in FIG. 9.

FIG. 11 is an explanatory diagram of an embodiment corresponding to thesecond feature of the present invention.

FIGS. 12A and 12B show an example of reading and writing operations of ageneral synchronous DRAM.

FIG. 13 is an embodiment corresponding to the third feature of thepresent invention to indicate an operational explanatory diagram oftransferring per a unit of a plurality of bytes.

FIG. 14 shows an operational timing chart corresponding to FIG. 13.

FIG. 15 shows one operational explanatory diagram of transferring of abyte boundary.

FIG. 16 shows an operational timing chart corresponding to FIG. 15.

FIG. 17 shows one operational explanatory diagram of transferring of abyte boundary.

FIG. 18 shows an operational timing chart corresponding to FIG. 17.

FIG. 19 shows other operational explanatory diagram of transferring byteboundary.

FIG. 20 illustrates an operational timing chart corresponding to FIG.19.

FIG. 21 illustrates another operational explanatory diagram fortransferring of a byte boundary.

FIG. 22 shows an operational timing chart corresponding to FIG. 21.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 4 shows an embodiment of the present invention, and shows a blockdiagram of the embodiment, when employing a data transferring deviceaccording to the present invention in a video game apparatus. Throughoutthe following descriptions, the same reference numerals are used todenote and identify corresponding or identical components.

In FIG. 4, an area 100 enclosed with a dotted line is a console unit ofthe video game apparatus.

A first bus (CPU-BUS) 5, a second bus (B-BUS) 6, and a third bus (A-BUS)8 are external buses for the data transferring device, and a CPU and amemory or the like are connected as a data transmitting and receivingdevice corresponding to each of the external buses. The datatransmitting and receiving device, as described above, is defined as acircuit device, which can transmit and receive data to and from the databus.

Further, the first bus (CPU-BUS) 5, the second bus (B-BUS) 6 and thethird bus (A-BUS) 8 are commonly connected to a system control unit 1.Throughout the latter described embodiments, the system control unit 1is corresponding to a data transferring device, which is an object ofthe present invention.

In the example shown in FIG. 4, the first bus (CPU-BUS) 5 includes a bussize of 32 bits, and each of the second bus (B-BUS) 6 and the third bus(A-BUS) 8 has a bus size of 16 bits.

In FIG. 4, a main CPU 2 includes a pair of high-speed CPUs to controlthe entire of the apparatus. A synchronous DRAM 3 is a work RAM employedby the main CPU2.

The system control unit 1 has a function for controlling each of theabove-described buses. A structural example of the system control unit 1will be explained later, as accompanied with FIG. 6.

Reference numerals 41 and 42 are first and second video displayprocessors (VDP).

The first VDP 41 has a function for controlling to display sprites ormodels on a screen. A video RAM 410 is connected to the first VDP 41.The video RAM 410 stores control commands for the first VDP 41 andcharacter data.

Further, frame buffer memories (FB) 411 and 412 are connected to thefirst VDP 41. Each of the FBs 411 and 412 has a duplexed bufferstructure, which is formed with a pair of memory devices. When writingimage data for one frame to one memory device, image data for anotherone frame may be read out from the other memory device.

The second VDP 42 controls scrolling of a picture on a screen anddetermines a priority order of displaying a picture on a screen. A videoRAM 420 is connected to the second VDP 42. The second video RAM 420stores a scrolling map, a bit map and coefficient data.

The main CPU 2 and the synchronous DRAM 3 are connected to the systemcontrol unit 1 via the first bus (CPU-BUS) 5. Meanwhile, the first andthe second VDPs 41 and 42 are connected to the system control unit 1 viathe second bus (B-BUS) 6.

Further, a cartridge 80 connected to the third bus (A-BUS) 8 is anexternal memory device, which is detachably connected to the consoleunit 100 of the video game apparatus, and has a memory element providedinside to store a game program. The third bus (A-BUS) 8 has the same bussize as that of the second bus (B-BUS) 6.

A CD-ROM drive unit 91 via an optical disk control unit 9 and further afunctional block, which generates an external image signal, such as MPEG(Moving Picture Expert Group), are connected to the third bus (A-BUS) 8.

A portion of the third bus (A-BUS) 8 may be extended to the outside ofthe console unit 100 of the video game apparatus. If a data transferringspeed becomes high, the FCC standard can not be fulfilled because ofsuch a problem that impediment radio waves are leaked. One of theobjects of the present invention is to solve such the problem.

A CPU controller 31, which is connected to the first bus (CPU-BUS) 5,arbitrates the first bus (CPU-BUS) 5, when a pair of high-speed CPUs 2access to the synchronous DRAM 3 and the system control unit 1.

The CPU controller 31 supervises controls when the CPU 2 accesses to anI/O controller (SMPC) 32 and a RAM/ROM 33. A control pad 30, which my bedetachably connected to the console unit 100 of the video game apparatusfrom the outside, is operated by a player.

Further, a converter circuit 401 converts an analog RGB signal, which isoutput from the second VDP 42, to a video signal. The video signal,which is output from the converter circuit 401 is displayed on a displaydevice 40.

A sound source processor 7 (SCSP) is connected to the second bus (B-BUS)6 to control the generation of PCM/FM sound. A CPU 70 for sound and aRAM 71 for work of the CPU 70 are connected to the-sound sourceprocessor 7, and the CPU controls the sound source processing.

Additionally, a D/A converter 8 is connected to the sound sourceprocessor 7 to convert a digital source to an analog signal and then tooutput an audio output.

A PLL circuit 20 generates a basic clock signal, which is supplied tothe entire system. As explained above, in the embodiment of the videogame apparatus shown in FIG. 4, the system control unit 1 is employed asa center circuit according to the basic clock from the PLL circuit 20,for interfacing between the different bus sizes of the first bus(CPU-BUS) 5, to which a main CPU 2 and a synchronous DRAM 3 areconnected, the second bus (B-BUS) 6, to which the first and second VDPs41 and 42 are connected, and the third bus (A-BUS), to which a memorycartridge is connected and which extends to the outside of the consoleunit 100 of the video game apparatus.

More particularly, a structural example of the first bus (CPU-BUS) 5,the second bus (B-BUS) 6 and the third bus (A-BUS) 8 will be explainedin accompanying with FIG. 5.

In FIG. 5, the first bus (CPU-BUS) 5 has the bus size of 32 bits, andthe CPU 2, the synchronous DRAM 3 and the CPU controller 31 areconnected to the first bus 5. The third bus (A-BUS) 8 has the bus sizeof 16 bits, to which the CD-ROM drive 91 and the cartridge 80 areconnected.

Further, the second bus (B-BUS) 6 has the bus size of 16 bits, to whichthe first and second VDPs 41 and 42, and the sound source processor 7are connected.

On the first through third buses 5, 6 and 8, data are transferred with abus clock of 28 MHz, which is based on the basic clock commonly suppliedfrom the PLL circuit 20.

FIG. 6 shows a detailed structural example of the system control unit 1as a data transferring device according to the present invention. FIGS.7 and 8 illustrate operation timing charts of the embodiment of thepresent invention. FIG. 7 shows the operation timing chart intransferring data from the first bus (CPU-BUS) 5 to the second bus(B-BUS) 6. FIG. 8 shows the operation timing chart in transferring datafrom the third bus (CPU-BUS) 8 to the second bus (B-BUS) 6 and theconcurrent operation status with the first bus (CPU-BUS).

In FIGS. 7 and 8, a numeral in the mark means a timing chart of a signalcorresponding to each part shown in FIG. 6.

In FIG. 6, the system control unit 1 includes a first bus interfacecircuit 11, a second bus interface circuit 12, a third bus interfacecircuit 14, and a direct memory access circuit (DMA) 10.

These circuits are connected by an internal bus 13 having the bus sizeof 32 bits, which is the same as that of the first bus (CPU-BUS) 5.Further, the first bus interface circuit 11 is connected to the firstbus (CPU-BUS) 5. The second bus interface circuit 12 and the third businterface circuit 14 are connected to the second bus (B-BUS) 6 and thethird bus (A-BUS) 8, respectively.

At first, data repetition from the first bus (CPU-BUS) 5 to the secondbus (B-BUS) 6 will now be explained (refer to FIG. 7).

The first bus interface circuit 11 is constituted with flip flops FF 110and 111, and tri-state buffers 112 and 113, which have TTLs, each havinga ternary logic. A basic clock CLK sent from the PLL circuit 20 (referto FIG. 7) is supplied to these circuits to regulate the operation.

When an input of the flip flop FF 110, i.e., a signal on the first bus(CPU-BUS) 5 is the data read out from the synchronous DRAM 3, the signalcontinuously appears as shown in 1 of FIG. 7. The continuous datadepends on a characteristic of the synchronous DRAM 3, in which inputand output signals are synchronized with a clock.

In the example shown in FIG. 7, it is controlled so as that one data iscontinuously outputted on the first bus (CPU-BUS) 5 per two periods ofthe basic clock CLK (1 FIG. 7). Accordingly, the tri-state buffer 112converts the output on the first bus to the timing signal shown in 2 ofFIG. 7 and the converted timing signal is output to the internal bus 13.

Meanwhile, the DMA 10 is constituted with flip flop circuits FF 101 and102, a selecting gate 103, and a tri-state buffer 104. The flip flop FF101 divides 32 bits of data sent from the internal bus 13 into groups of8 bits, and inputs the divided groups of 8 bits to the selecting gate103 via the buses B1 through B4.

The flip flop circuit FF 102 receives the divided upper three groupssent from the flip flop circuit FF 101 and outputs them to the selectinggate 103. The selecting gate 103 has four input terminals 0 to 3. Thedata of 32 bits, which are divided and subsequently shifted per 8 bits,are inputted to each of the input terminals 0 to 3.

The selecting gate 103 selects and outputs the input of the four inputterminals 0 to 3 according to the selecting signal S5, and outputs themto the internal bus 13 through the tri-state buffer 104. Then, theoutput from the DMA 10 is shown with a timing shown in 3 of FIG. 7.

As shown in FIG. 7, a timing of the output from the DMA 10 (3 of FIG. 7)is shifted by one clock of the basic clock for a timing of the data (2of FIG. 7) outputted from the first bus interface circuit 11.Accordingly, it is possible to prevent from collision of the data (2 and3 of FIG. 7) on the internal bus 13.

Additionally, the second bus interface circuit 12 takes the dataoutputted from the DMA 10 into the internal bus 13. The second businterface circuit 12 is constituted with flip flop circuits FF 120, 122,124 and 125, a selecting gate 121, and tri-state buffers 123 and 126.

The flip flop FF 120 of the second bus interface circuit 12 takes thedata on the internal bus 13 with a timing for two periods of a basicclock CLK (4 of FIG. 7).

Further, the selecting gate 121 alternatively selects and outputs theupper 16 bits (A'H) and the lower 16 bits (B'H), and outputs them to thesecond bus (B-BUS) 6 via the flip flop FF 122 and the tri-state buffer123 (5 of FIG. 7).

A case where the operation on the first bus (CPU-BUS) can be performedconcurrently with transferring data on the third bus (A-BUS) 8 to thesecond bus (B-BUS) 6 will now be described.

The data on the third bus (A-BUS) 8 are generated by synchronizing pertwo periods of the basic clock CLK (6 of FIG. 8). The third businterface circuit 14 takes the data on the third bus (A-BUS) 8 as theupper and lower data (7 and 8 of FIG. 8).

That is, the third bus interface circuit 14 has the same structure ofthat of the second bus interface circuit 12. The data on the third bus(A-BUS) 8 are alternatively inputted to a pair of flip flops FF 143 and144. The outputs of the flip flops FF 143 and 144 are composed as thedata of 32 bits via the tri-state buffer interface circuit 145 and takento the internal bus 13 (9 of FIG. 8).

The DMA 10 receives and shifts the data of 32 bits taken to the internalbus 13 by one basic clock, and again outputs the shifted data of 32 bitsto the internal bus 13 3 of FIG. 8). The second bus interface circuit 12takes the output signal with 4 basic clock periods (4 of FIG. 8).

Further, the second bus interface circuit 12 the upper data (A'H) andthe lower data (A'L) respectively of 16 bits with a basic clock CLKperiod (1 of FIG. 8).

Simultaneously with the above-described operation, it becomes possibleto operate the independent data (C1, C2 . . . ) of 32 bits with a periodof the basic clock CLK on the first bus (CPU-BUS) (1 of FIG. 8).

As explained above, according to the present invention, it becomespossible to transfer data between the data transmitting and receivingdevices connected to the buses, the bus sizes of which are different.Additionally, there is no need to provide any bus interface circuit,which interfaces with the CPU bus 5 in each data transmitting andreceiving device connected to a corresponding data bus, because thesystem control unit 1 has internal bus interface circuits, each providedfor each data transmitting and receiving device.

FIG. 9 illustrates a detailed embodiment, in which the data sent via thefirst bus (CPU-BUS) 5 are transferred via the second bus (B-BUS) 6having a limited bus size by accessing the first VDP 41 or the secondVDP 42.

In FIG. 9, the system control unit 1 is shown as an example oftransferring data to the first VDP 41.

In order to access and transfer the data sent via the first bus(CPU-BUS) 5 from the system control unit 1 to the corresponding firstVDP 41, it is required to transmit address, data, and read/writedistinguishing signals.

An address signal is constituted with 20 bits of A0 to 19 (20 signallines are necessary), a data has 16 bits of D0 to 15 (16 signal linesare necessary), and further, a Read/Write distinguishing signal has aR/W bit (one signal line is necessary). The total lines required arethen 37 signal lines.

Further, although the explanation has been abbreviated in FIGS. 4 and 6,there are necessary a chip select signal (CS), which indicates whetheror not the system control unit 1 accesses to the VDP 41 (0)/(1), and adata enabling signal (DTEN), which indicates whether or not the data onthe second bus (B-BUS) 6 is valid (0)/(1).

Accordingly, the above-described control signals (CS and DTEN) showingthe chip selection and the data validity are generated and sent to thetwo signal lines L1 and L2 as shown in FIG. 9.

Meanwhile, the second bus (B-BUS) 6, which connects the system controlunit 1 with the first VDP 41 and the second VDP 42 has the bus size of16 bits. Accordingly, in the embodiment shown in FIG. 9, the second bus(B-BUS) 6 connecting the system control unit 1 and the first VDP 41 has16 signal lines or the bus size of 16 bits, and there are furtherprovided two control signal lines (for control signals CS and DTEN)between the system control unit 1 and the first VDP 41.

When the system control unit 1 accesses to the first VDP 41, the systemcontrol unit 1 makes the chip select signal line (CS) to LOW (0), andsimultaneously divides the addresses into the upper and lower addressesto transmit them to the second bus (B-BUS) 6.

After then, when writing to the first VDP 41, the write data of 16 bitsare sent as data 1 (DD1), data 2 (DD2), data 3 (DD3) . . . Further, eachdata is transmitted to the first bus (B-BUS) 6 per one clock CLK.

The content of the above-described B-BUS 6 is shown in FIG. 10A. In FIG.10A, B15 to B0 are signal line bits of 16 bits, and the mark "-" means aunused bit. The first bus (B-BUS) 6 is divided into H1, H2, DD1, DD2 . .. according to the content.

The address is divided to the upper 12 bits (H1) and the lower 8 bits(H2), and the upper 12 bits (H1) and the lower 8 bits (H2) are sent out.Further, a read/write signal RW is allocated to the remaining bits ofthe upper address H1. The data (D15 to D0) of 16 bits are allocated toafter the DD1.

The first VDP 41 acknowledges the data are addressed to itself by thechip select signal CS transmitted from the system control unit 1, andthen takes the data transmitted to itself. When the processing ofreading data from the first VDP 41, the VDP 41 takes the address, whichare divided into upper and lower addresses, and transmits required datato the second bus (B-BUS) 6.

The system control unit 1 receives the data transmitted from the VDP 41via the second bus (B-BUS) 6 and transmits them to the first bus(CPU-BUS) 5 or the third bus (A-BUS) 8 via the bus interface circuits12, 11 and 14 and the DMA 10, as described above.

It is possible to transfer addresses and data between the system controlunit 1 and the first VDP 41, similarly or the second VDP 42 via theabove-described second bus (B-BUS) 6 of 16 bits.

Further, the operation of the control signals on two control signallines L1 and L2 respectively for signals CS and DTEN and the second bus(B-BUS) 6 will now be explained in accompanying with a timing chart.FIG. 10B shows the timing chart showing the operation of the second bus(B-BUS) 6.

In FIG. 10B, T1 to T8 . . . express leading timings of the clock CLKwith time flow. H1 and H2 show the upper and the lower addresses on thesecond bus (B-BUS) 6, respectively. DD1 to DD4 are respective data onthe second bus (B-BUS) 6.

In FIG. 10B showing the timing chart of the B-BUS 6, at first a chipselect signal CS is turned to LOW (0)! with a timing T2 of the clockCLK. Simultaneously, within the period of timings T2 to T3, the systemcontrol unit 1 sends the upper address H1 to the second bus (B-BUS) 6.Subsequently, within the period of timings T3 to T4, the lower addressH2 is sent.

When writing from the system control unit 1 to the first VDP 41, dataDD1, DD2, DD3 and DD4 are sent from the system control unit 1 to thesecond bus (B-BUS) 6 per one clock of the clock CLK, following thetiming T4. Simultaneously, the DTEN signal showing data validity isturned to LOW (0)!. The VDP 41 takes the H1, H2, DD1 . . . inside at anytime. After DD1, it is possible to write data only when the DTEN signalshowing data validity is LOW (0)!.

Accordingly, where the transferring of data can not be performed withina certain period, the system control unit 1 makes the DTEN signalshowing data validity to HIGH (1)!, and then the writing operation isabbreviated for the first VDP 41.

In the example of FIG. 10B, it is possible to output the data DD4 ontiming Tm. Therefore, the system control unit 1 makes the DTEN signalshowing data validity to LOW (0)! again, and simultaneously, outputsdata DD4 within the period of timings Tm to Tm+1.

FIG. 10B shows an example of writing four data of DD1 to DD4. The chipselect signal CS becomes HIGH (1)! with timing Tm+1 to finish writing tothe VDP 41.

Meanwhile, when reading out from the first VDP 41, the data DD1, DD2,DD3 and DD4 are outputted from the VDP 1 per one clock of the clock CLK,following the timing T4.

In this case, the DTEN signal showing data validity transmitted from thesystem control unit 1 is ignored, and the continuous data DD1, DD2, DD3and DD4 are taken in the system control unit 1 at any time.

If a constant number of data read processing is finished, the systemcontrol unit 1 makes the chip select signal CS to HIGH (1)! to finishthe data read accessing.

Further, a case where the data read out from a RAM connected to thefirst bus (CPU-BUS) 5 to a RAM connected to the second bus (B-BUS) 6will be now considered. In this case, as described according to theexplanation of FIG. 4, the synchronous DRAM 3 is employed as the RAMconnected to the first bus (CPU-bus) 5. This is the second feature ofthe present invention, and it is possible to transfer data withemploying a characteristic of the synchronous DRAM 3, from which datamay be continuously read out.

FIG. 11 shows a concept structure of a video game apparatus, in whichthe second feature according to the present invention is applied,similarly to the examples shown in FIGS. 4 and 6.

Therefore, the same reference numerals are used to denote and identifycorresponding or identical numerals shown in FIGS. 4 and 6.

In comparison with the structure shown in FIG. 4, a basic structureshown in FIG. 11 according to the second feature of the presentinvention corresponds to the structure shown in FIG. 4, which includesthe system control unit 1, the CPU 2, the synchronous DRAM 3, the firstand second VDPs 41 and 42, the sound source processor 7, and the firstbus (CPU-BUS) 5 and the second bus (B-BUS) 6 connecting theabove-described circuits.

Further, a first bus interface circuit 11, a second bus interfacecircuit 12, and a direct memory access circuit (DMA) 10, whichconstitutes the system control unit 1 shown in FIG. 11 corresponds tothe first bus interface circuit 11, the second bus interface circuit 12,and the direct memory access circuit (DMA) 10 shown in FIG. 6.

The third bus interface circuit 14 connected to the internal bus 13disclosed in FIG. 6 is not shown in FIG. 11. This is because thestructure of the third bus interface circuit 14 is the same as that ofthe second bus interface circuit 12, as the third bus interface circuit14 is connected to the internal bus 13 of 32 bits and the external busof 16 bits.

In FIG. 6, when data of 16 bits are transmitted from the second andthird buses 6 and 8, which are respectively connected to the second andthird bus interface circuits 12 and 14 to the first bus (CPU-BUS) 5, theflip flop circuits FF 124 and 125 and the tri-state buffer 126 in thesecond bus interface 12 compose two continuous data of 16 bits to dataof 32 bits and output them to the internal bus 13. Further, the flipflop circuits FF 143 and 144 and the tri-state buffer 145 in the thirdbus interface 13 compose and output the data by the same way as in thesecond bus interface 12 to the internal bus 13.

The data of 32 bits outputted to the internal bus 13 are transmitted tothe first bus (CPU-BUS) 5 via the DMA 10, the flip flop circuit FF 111and a tri-state buffer 113 in the first bus interface circuit 11, asdescribed above.

The synchronous DRAM 3 has a characteristic of making input and outputsignals be synchronized with a clock, and continuously reading andwriting the signal data in addition to a characteristic of theconventional DRAM. As one example of the characteristic is shown inFIGS. 12A and 12B, the synchronous DRAM 3 synchronizes the operation ofthe conventional DRAM with a clock.

FIG. 12A shows a read operation of a general synchronous DRAM includingthe synchronous DRAM 3, and FIG. 12B shows a timing chart showing thewrite operation. The read and write operations are performed accordingto the control signals /RAS, /CAS and /WE.

These input signals as a control signal, are taken into by synchronizingon leading timings of the synchronous clocks CLK. A cycle period of theclock CLK is 10 ns, the clock frequency is 100 MHz. Therefore, itbecomes possible to take into the input signals synchronized with theclock.

As the content of the timing chart is not directly related to theexplanation of the present invention, detailed explanation is omitted.But, it can be understood from FIGS. 12A and 12B to continuously outputand write data as indicated by DQs, which are read and write data,respectively.

In this way, data reading and writing operation is continuouslyperformed as a feature of the synchronous DRAM. In the presentinvention, the synchronous DRAM is employed as a RAM, as described inFIG. 11. With the structure of the DMA 10 shown in FIG. 6, it ispossible to provide data transferring device employing the feature ofthe synchronous DRAM.

Further, on the explanation of the second feature, although a case wherethe data of 32 bits on the first bus are divided into two sets of thedata of 16 bits and sent to the second bus, the present invention is notrestricted to this, and it is also possible to divide data of 32 bitsinto 1/n (n is positive integral) and send out divided data.

In the conventional device, there has been a problem of increasingaccess times, i.e., low speed in the DMA transferring operation, whenstarting to write data from the byte boundary, and writing per a byte.The third feature of the present invention is to solve theabove-described problem, and it will now be explained.

The third feature of the present invention is realized in the DMA 10provided in the system control unit 1 of the embodiments shown in FIGS.3 and 6.

The third feature of the present invention will be again explained inaccompanying with a structure of the system control unit 1 shown in FIG.6. Further, as the third interface circuit 14 has the same structure asthe second interface circuit 12, as explained above, the duplicatedexplanation about the third interface circuit 14 will be omitted forsimplicity.

In FIG. 6, the first interface circuit 11 includes a first latch circuit(flip flop) 110, which latches the signal S1 of 32 bits, a tri-statebuffers 112, 113, which output ternary logic signals, and a second latchcircuit 111, which latches the signal of 32 bits on the internal bus 13.

The second interface circuit 12 includes a first latch circuit 120,which latches data S6 of 32 bits on the internal bus 13, a selector 121,which receives and converts the parallel data S6 of 32 bits latched byand output from the first latch circuit 120 to a pair of data of 16bits, a second latch circuit 122, which latches the data of 16 bitsoutput from the selector 121 and a tri-state buffer 123, which receivesthe data of 16 bits latched by the second latch circuit 122 and outputsternary logic signals to the second bus (B-BUS) 6.

Since the second interface circuit 12 transmits data on the second bus(B-BUS) 6 to the internal bus 13, the second interface circuit 12includes a pair latch circuits 124 and 125 for data of 16 bits and atri-state buffer 126, which composes the data of 16 bits latched by thepair latch circuits 124 and 125 and outputs data of 32 bits to theinternal bus 13.

The DMA 10 includes a first latch circuit (flip flop) 101, which latchesdata of 32 bits on the internal bus 13, a second latch circuit (flipflop) 102, which latches the lower 3 bytes (24 bits) of the data, aselector 103, which receives combined signals of the outputs from thefirst and second latch circuits 101 and 102, selects and outputs theoutputs according the selecting signal S5 supplied at the selectingterminal S, and a tri-state buffer 104, which receives and outputs theoutput from the selector 103 to the internal bus 13.

The selector 103 has four input terminals and one output terminal. Thatis, the output lines B1 to B4 of four bytes of the first latch circuit101 are connected to the first input terminal 0 of the selector 103. Theupper three bytes of the output lines B1 to B3 of the first latchcircuit 101 and the lower one byte of the output line B7 of the secondlatch circuit 102 are connected to the second input terminal 1 of theselector 103.

The upper two bytes of the output lines B1 to B2 of the first latchcircuit 120 and the lower two bytes of the output lines B6 to B7 of thesecond latch circuit 101 are connected to the third input terminal 2 ofthe selector 103. The upper one byte of the output line B1 of the firstlatch circuit 101 and the lower three bytes of the output lines B5 to B7of the second latch circuit 102 are connected to the fourth inputterminal 3 of the selector 103. Accordingly, the data of four bytes,which are not shifted, are inputted to the first input terminal 0. Thedata of four bytes, which are shifted by one byte, are inputted to thesecond input terminal 1. The data of four bytes, which are shifted bytwo bytes, are inputted to the third input terminal 2. The data of fourbytes, which are shifted by three bytes are inputted to the fourth inputterminal 3.

Therefore, if the selecting signal S5 selects the first input terminal0, transmission from a long-word boundary (refer to FIGS. 3A and 3B)will be performed as shown in FIGS. 13 and 14, which will be laterdescribed. Further, if the selecting signal S5 selects the second inputterminal 1, transmission to the byte boundary, which is shifted by onebyte, as shown in FIGS. 15 and 16, will be performed.

Furthermore, if the selecting signal S5 selects the third input terminal2, transmission to the byte boundary, which is shifted by two bytesshown in FIGS. 17 and 18, which will be later explained, will beperformed.

If the selecting signal S5 selects the fourth input terminal 3,transmission to the byte boundary, which is shifted by three bytes shownin FIGS. 19 and 20, will be performed.

DMA transmission operation according to the third feature of the presentinvention will now be explained in accompanying with FIGS. 13 to 22.

At first, as shown in FIG. 13, a long-word boundary transmission will beexplained as follows, which is to transmit the data "A B C D E F G H" of8 bytes, that is, 32 bits on the addresses (0000h to 0007h) of the RAM3, which corresponds to the SDRAM 3 shown in FIG. 4, on the first bus(CPU-BUS) 5 to the corresponding addresses (0000h to 0007h) of the RAM420, which corresponds to the VRAM 420 connected to the VDP 42 in FIG. 2on the second bus (B-BUS) 6 via the system control unit 1.

As shown in FIG. 14, it is controlled that the 4 bytes of data S1 areoutputted per two clocks on the first bus (CPU-BUS) 5. The data S1 isoutputted to the internal bus 13 at the timing of t1 (signal S2). Then,the parallel data S2 of four bytes on the internal bus 14 are latched bya first latch circuit 101 in the DMA 10 at the timing of t2 (signal S3).

The output S3 of the first latch circuit 101 is latched by the secondlatch circuit 102 at the timing of t4 (signal S4). Then, the selectingsignal S5 for the selector 103 indicates the first input terminal 0 inorder to transfer from the long-word boundary.

Accordingly, the selector 103 selects the data "ABCD" of four byteslatched in the first latch circuit 101 to output the data as data S6.The second interface circuit 12 takes the data S6 into the latch circuit120 at the timing of t3.

As the second bus (B-BUS) 6 is 16 bits, as shown with the signal S8, theselector 121 and the latch circuit 122 convert the data of 32 bits totwo serial data sets, each of which has 16 bits. The data are outputtedto the second bus (B-BUS) 6 via the tri-state buffer 123.

In this way, each data unit having a plurality of bytes is written fromthe long-word boundary as shown in FIG. 14.

Similarly to FIG. 13, when the data, of which addresses are 0000h to0007h, of the RAM 3 on the first bus (CPU-BUS) 5 are transferred to theRAM 420, of which addresses are 0001h to 0008h, on the second bus(B-BUS) 6, the DMA transmission starting from a byte boundary, which isshifted by one byte, in this example, as shown in FIG. 15 will be nowexplained.

As shown in FIG. 16, the data S1 of four bytes is outputted per twoclocks on the first bus (CPU-BUS) 5. The data S1 is outputted to theinternal bus 13 at the timing of t1 (signal S2). Then, the four bytes ofparallel data S2 on the internal bus 13 is latched in the first latchcircuit 101 of the DMA 10 at the timing of t2 (signal S3).

The lower three bytes of the output data S3 from the first latch circuit101 are latched in the second latch circuit 102 at the timing of t4(signal S4). Because of a transmission from a byte boundary, which isshifted by one byte, the selecting signal S5 of the selector 103indicates the second input terminal 1.

Accordingly, the selector 103 selects the data "ABC" of the upper threebytes (lines 1 to B3) in the first latch circuit 101 and the data of thelower one byte (line B7) in the second latch circuit 102 and outputsthem as data S6, which is "xABC". "x" means data is unsettled.

In the second interface circuit 12, the latch circuit 101 takes the data"XABC" at the timing of t3. Then, as the second bus (B-BUS) 6 has thebus size of 16 bits, as shown with the signal S8, the selector 102 andthe latch circuit 122 convert the data of 32 bits to two serial data of16 bits. The data are then outputted to the second bus (B-BUS) 6 via atri-state buffer 123.

Simultaneously, at the timing of t4, the first latch circuit 101 of theDMA 10 latches the parallel data S2, "EFGH" of four bytes on the outputterminal.

Therefore, the selector 103 selects the upper data "EFG" (lines B1 toB3) of 3 bytes of the first latch circuit 101 and the lower data "D"(line B7) of one byte and outputs them as data S6. Accordingly, the dataare "DEFG".

In this way, writing per a unit having a plurality of bytes will bestarted from the byte boundary, which is shifted by one byte, as shownin FIG. 15.

Next, as shown in FIG. 17, the DMA transmission starting from a byteboundary, which is shifted by two bytes, will be explained which is totransmit data (0000h to 0007h) of the RAM 3 (0000h to 0007h) on thefirst bus (CPU-BUS) 5, to the RAM 420 (0002h to 0009h) on the second bus(B-BUS).

As shown in FIG. 18, the data S1 of four bytes are outputted per twoclocks on the first bus (CPU-BUS) 5. The data S1 is outputted to theinternal bus 13 at the timing of t1 (signal S2). Then, the first latchcircuit 101 of the DMA 10 latches the parallel data S2 of four bytes onthe internal bus 13 at the timing of t2 (signal S3).

The second latch circuit 121 latches the data of lower three bytes ofthe output S3 from the first latch circuit 101 at the timing of t4(signal S4). Because the transmission is started from the byte boundary,which is shifted by two bytes, the selecting signal S5 of the selector103 indicates the third input terminal 2.

Accordingly, the selector 103 selects the upper data "AB" (lines B1 toB2) of two bytes latched in the first latch circuit 101 and the lower 2bytes (lines B6 to B7) in the second latch circuit 102, and outputs themas data S6. The data are "xxAB". "x" means the data are unsettled as thesame as the above-described example.

In the second interface circuit 12, the latch circuit 120 takes the dataat the timing of t3. Then, as the second bus (B-BUS) 6 has the bus sizeof 16 bits, as shown with the signal S8, the selector 121 and the latchcircuit 122 convert the data of 32 bits to two serial data of 16 bits.The data are outputted to the second bus (B-BUS) 6 via a tri-statebuffer 123.

Simultaneously, the first latch circuit 101 in the DMA 10 latches theparallel data S2, i.e., data "EFGH" of four bytes on the internal bus 13(signal S3) at the timing of t4.

Therefore, the selector 103 selects the data "EF" (lines B1 to B2) ofupper 2 bytes in the first latch circuit 101 and the data "CD" (lines B6and B7) of lower 2 bytes in the second latch circuit 102 and outputsthem as data S6. The data are "CDEF".

In this way, writing per a unit of a plurality of bytes started from thebyte boundary, which is shifted by two bytes, shown in FIG. 17, isperformed.

As shown in FIG. 19, DMA transmission starting from the byte boundary,which is shifted by three bytes, will be explained as follows. By theDMA transmission, the data (0000h to 0007h) of the RAM 3 on the firstbus (CPU-BUS) 5 are transferred to the RAM 420 on the B-BUS 6.

As shown in FIG. 20, the data S1 of four bytes are outputted on thefirst bus (CPU-BUS) 5 per two clocks. The data S1 are then outputted tothe internal bus 14 at the timing of t1 (signal S2). Then, the firstlatch circuit 101 latches the 4 bytes of parallel data S2 of four byteson the internal bus 13 at the timing of t2 (signal S3).

The second latch circuit 102 latches the lower data of three bytes ofthe output S3 latched in the first latch circuit 101 at the timing of t4(signal S4). Because transmission is started from a byte boundary, whichis shifted by three bytes, the selecting signal S5 of the selector 103indicates the fourth input terminal 3.

Therefore, the selector 103 selects the upper data (line B1) of one bytein the first latch circuit 101 and the lower data (lines B5 to B7) ofthree bytes in the second latch circuit 102, and outputs them as dataS6. The data are "xxxA". "x" means data is unsettled.

In the second interface circuit 12, the latch circuit 120 takes the dataat the timing of t3. Then, the second bus (B-BUS) 6 has the size of 16bits, as shown with the signal S8, the selector 121 and the latchcircuit 122 convert the data of 32 bits to two serial data of 16 bits.The data are outputted to the second bus (B-BUS) 6 via a tri-statebuffer 123.

Simultaneously, the first latch circuit 101 of the DMA 10 latches theparallel data S2 of four bytes on the internal bus 13, i.e., data"EFGH", at the timing of t4 (signal S3).

Therefore, the selector 103 selects the upper data "E" (line B1) of onebyte in the first latch circuit 101 and the lower data "BCD" (lines B5to B7) of three bytes in the second latch circuit 121 and outputs themas data S6. The data are "BCDE".

In this way, writing per a unit having a plurality of bytes is startedfrom the byte boundary, which is shifted by three bytes, as shown inFIG. 19.

FIG. 21 shows an explanatory diagram of transferring DMA started fromthe byte boundary, which is shifted to 1 byte, which is to transmit thedata (0002h to 0009h) of the RAM 3 on the first bus (CPU-BUS) 5 to theRAM 420 (0003h to 000Ah) on the second bus (B-BUS) 6.

It is apparent from FIG. 22 that the operation of the example in FIG. 21is basically the same as that shown in FIG. 16. In this way, even if thedata of the RAM 1, i.e., SDRAM 3, are shifted from the long-wordboundary, the data can be transferred per a unit having a plurality ofbytes to the byte boundary position shifted from the long-word boundary.

The above-described RAM 2 corresponds to the VRAM 420 in FIG. 2, i.e., abit map memory, which expresses one pixel with one byte. In this case,for example, it is effective for subsequently shifting and displayingmoving pictures to start writing from an optional byte boundary. Then,in the case employing the present invention, it can be realized with, atmost, 5 times of accessing to transfer data for 16 pixels. In theconventional transmission per a byte, it is required to access 16 times.Therefore, the times of transferring becomes less than about 1/3, sothat the transferring can be performed with a high speed for displayingvideo image.

Further, some variations can be applied to the above-described thirdfeature of the present invention as follows;

Although a unit byte number n of the long word is 4, other number may beemployed.

The second memory is explained as a bit map memory. However, othermemory may be applied. Further, the second memory has the size of 16bits, but the memory having the size of 32 may also be applied.

Although the B-BUS has the size of 16 bits in the embodiment of thepresent invention, the bus of 32 bits may be employed.

As explained according to the embodiments, a data transferring device,which can simultaneously transfer data between a plurality of datatransmitting and receiving devices may be obtained.

Further, a data transferring device, which has no need to provide aninterface circuit interfacing to a high-speed CPU via a datatransmitting and receiving device may be obtained, even if bus sizes ofa plurality of data transmitting and receiving devices are different.

Furthermore, according to the present invention, a video game apparatusemploying a data transferring device is realized, which may employ ahigh-speed CPU.

Additionally, it becomes possible to transfer data, as employing acharacteristic of a synchronous DRAM, which can continuously read outdata. Even if a data transferring device writes data from the byteboundary to the bit map memory, the data transferring device employing aDMA may reduce times of accessing according to the present invention.

A data transferring device employing the DMA, which can reducetransferring time when writing data from the byte boundary can be alsorealized.

Although the present invention has been described with reference toembodiments, when applying to a structure of a video game apparatus, thepresent invention is not restricted to those.

It should of course be understood that those which are the same as thetechnical concept of the invention are within the protective scope ofthe present invention.

What is claimed is:
 1. A data transferring device, which is connected toa plurality of data transmitting and receiving devices via correspondingexternal buses, for transferring data between the plurality of the datatransmitting and receiving devices comprising:a plurality of businterface circuits, to which each of the corresponding external buses isconnected; and a direct memory access circuits operatively connected tothe plurality of bus interface circuits by an internal bus fortransferring the data between the plurality of bus interface circuits.2. The data transferring device according to claim 1,wherein at leasttwo of the plurality of bus interface circuits are respectivelyconnected to external buses, each having a different bus size from thatof the other, the internal bus has a bus size corresponding to themaximum one within the bus sizes of said external buses, and a dataprocessing circuit for dividing or uniting data to accord with the bussize of either one, to which the data are transferred, of the externalbuses, when the data are transferred between the external buses, eachhaving different bus sizes.
 3. The data transferring device according toclaim 2,wherein the data processing circuit divides data on a firstexternal bus having a first bus size and sequentially transfers thedivided data to a second external bus having a second bus size, which issmaller than the first bus size, according to a plurality of timings. 4.The data transferring device according to claim 2,wherein the dataprocessing circuit unites data for a plurality of timings on a secondexternal bus having a second bus size and sequentially transfers theunited data to a first external bus having a first bus size, which islarger than the second bus size.
 5. An information processing apparatus,comprising:a data transferring device, which is connected to a pluralityof data transmitting and receiving devices via corresponding externalbuses, for transferring data between the plurality of the datatransmitting and receiving devices, said data transferring deviceincluding a plurality of bus interface circuits, to which each of thecorresponding external buses is connected, wherein at least two of theplurality of bus interface circuits are respectively connected toexternal buses, each having a different bus size from that of the other,and a direct memory access circuit, operatively connected to theplurality of bus interface circuits by an internal bus, for transferringthe data between the plurality of bus interface circuits, and wherein atleast one of the plurality of the bus interface circuits is connectedwith a data transmitting and receiving device via an external bus fromthe outside of the information processing apparatus, and the bus size ofthe external bus connected to the data transmitting and receiving devicehas the minimum size within the external buses connected to the datatransferring device.
 6. A data transferring device connected to a firstexternal bus and a second external bus having 1/n (n means positiveinteger) of the bus size of the first external bus, comprising:first andsecond bus interface circuits, to which the first and second externalbuses are respectively connected; a direct memory access circuit fortransferring data on the first external bus, which are transmitted tothe first bus interface circuit, to the second bus interface circuit;and an internal bus connected to the first and second bus interfacecircuits and the direct memory access circuit, having the same bus sizeas that of the first external bus, the first bus interface circuitconverting the data, which are continuously transmitted with apredetermined period synchronized with a clock signal, on the firstexternal bus to the data having 1/n of the predetermined period andoutputting the converted data to the internal bus, the direct memoryaccess circuit shifting the data by a 1/n period and re-transmitting theshifted data to the internal bus, and the second bus interface circuittaking the data of 1/n of the predetermined period, which arere-transmitted from the direct memory access circuit to the internalbus, making the taken data to a continuous data sequence with the 1/nperiod, and re-transmitting the continuous data sequence with the 1/nperiod to the second external bus.
 7. The data transferring deviceaccording to claim 6, wherein the positive integer n is
 2. 8. The datatransferring device according to claim 7,wherein the second interfacecircuit makes data, taken in the direct memory access circuit, on thefirst external bus, to upper and lower data, which respectively are onehalf data sequence of the data and transfers the upper and lower data tothe second external bus.
 9. The data transferring device according toclaim 6, further comprising a synchronous DRAM, of which inputs andoutputs are synchronized with a clock, connected to the first externalbus to read data output from the synchronous DRAM and send the data tothe first bus interface circuit.
 10. A video game apparatus comprising:aCPU for executing a game program; a first video display processor forcontrolling displayed models or sprites on a picture plane; a secondvideo display processor for controlling a scroll of the picture planeand determining priority of displayed pictures; and a system controlunit connected to the CPU, each of the first and second video displayprocessors, through corresponding external buses, including, a first businterface circuit, to which the CPU is connected, a second bus interfacecircuit, to which the first and second video display processors areconnected, and a direct memory access circuit for transferring data,which are transmitted to the first bus interface circuit, to the secondbus interface circuit.
 11. The video game apparatus according to claim10, further comprising,a storage memory device provided outside of aconsole unit and connected to the system control unit for storing a gameprogram, which is executed by the CPU.
 12. A direct memory accesscircuit, which reads in and transfers data per a plurality of n bytes,comprising:a first latch circuit for latching n bytes of data, which areread in; a second latch circuit operatively connected to the first latchcircuit for latching (n-1) bytes of the data output from the first latchcircuit; and a selector supplied with the n bytes of data latched in thefirst latch circuit and combined n bytes, which are formed by combiningthe latched n byte data of the first latch circuit with the latched(n-1) byte data of the second latch circuit and shifting sequentially byone byte, for selecting a desired set of n bytes of data from thesupplied n bytes.
 13. The direct memory access circuit according toclaim 12, wherein a destination, to which the data selected by theselector is transferred is a bit map memory.
 14. The direct memoryaccess circuit according to claim 12, wherein the selected set of nbytes of data by the selector is transferred to a memory wherein eachone pixel is expressed with one byte.